1. Field of the Invention
The present invention relates to a metallization and bonding process for manufacturing power semiconductor devices.
2. Discussion of the Related Art
In the last few years, a fast technological evolution in the field of power semiconductor devices has made available, among other things, power MOSFETs with low "ton" resistance (R.sub.DS(on)) and Power Integrated Circuits (PICs) for performing complex functions and capable of switching rather high power values.
PICs are characterized by high component counts, i.e., a high integration density; the metal layers should therefore allow for a high interconnection density and introduce low series resistance. Because these two requirements conflict, a trade off value for the thickness of the metal layer must be found. Such thickness values are generally so low that dedicated areas on the die surface, distinct from the active areas where the various components are defined, have to be reserved for the attachment (bonding) of leads to the die, because otherwise the leads could perforate the metal layer and damage the underlying integrated circuit. As a result the device area increases, and parasitic resistances due to the necessity of long interconnection lines between the active area and the bonding region are introduced.
Power MOSFETs are less sensitive to integration density problems, but it is extremely important to minimize all parasitic resistances so that low values of the R.sub.DS(on) may be attained, by bonding the leads directly on the active area. To prevent the bonding wires from perforating the metallization, this layer should have a rather high thickness, typically greater than 3 .mu.m. Such a thick layer results in problems in both manufacturing and reliability, because the step coverage characteristics of a layer by a superimposed layer gets worse as the step height increases.
To prevent damage in the bonding process, the maximum diameter of a bonding wire is generally determined by the metallization layer thickness. To avoid the parasitic resistance of the bonding wire from affecting the MOSFET R.sub.DS(on), it is possible to bond in parallel two or more wires of smaller diameter, but at an increased cost.